![]() To make the comparator simple my own preference is to design a down-counter which is loaded with the target value on (p)reset. To achieve a low and synchronized delay after the event, set the target value that you wish to compare with to the value that occurs 1 cycle before the event occurs, then delay the result 1 cycle with a flip-flop. It should be possible to design a very wide counter. If you feed that to the Count enable input (CEP) of the next counter you synchronize the counters. With the 4-bit ICs you already have, you have a terminal count (TC) output. This can easily be done in an FPGA but I don't think you need anything that complex for what you describe. Is there a better solution to this problem? I am willing to try using a CPLD/FPGA to make a huge synchronous counter, but I have no experience and don't know how many gates/logic units are required. However I end up having to cascade at least 8 of them, which approaches their propagation delay limits (I calculate a max frequency of 11MHz). Right now I am prototyping with 4-bit counters like the 74LVC161. ![]() The interrupt has to occur very fast, before the next event (so less than 100ns), which is why I'm using discrete logic instead of a microcontroller. I will use it to count a succession of events, and give an interrupt when the count reaches a specified value. preferably, a built-in preset or compare function.I am looking for a counter/timer IC with the following capabilities: I am looking for the right technique to construct a very fast counter. EDIT: Just to be clear this is not intended to be a "shopping" question.
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